View AM29BDS643GT5KVAI_1935942.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication number 25692 revision a amendment 2 issue date may 8, 2006 am29bds643g data sheet retired product this product has been retired and is not recomm ended for designs. for new designs, s29ns064j supersedes am29bds643g. please refer to the s29n s-j family data sheet for specifications and ordering information. availability of this document is retained for referenc e and historical purposes only. the following document contains inform ation on spansion memory products. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary. for more information please contact your local sales office for additi onal information about spansion memory solutions.
this page left intentionally blank.
data sheet publication# 25692 revision: a amendment: 2 issue date: may 8, 2006 am29bds643g 64 megabit (4 m x 16-bit) cmos 1.8 volt-only simultaneous r ead/write, burst mode flash memory distinctive characteristics single 1.8 volt read, program and erase (1.7 to 1.9 volt) multiplexed data and address for reduced i/o count ? a0?a15 multiplexed as d0?d15 ? addresses are latched by avd# control input when ce# low simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations read access times at 66/54/40 mhz ? burst access times of 11/13.5/20 ns @ 30 pf at industrial temperature range ? asynchronous random access times of 55/70/70 ns @ 30 pf ? synchronous random access times of 71/87.5/95 ns @ 30 pf burst length ? continuous linear burst ? 8/16/32 word linear burst with wrap around power dissipation (typical values, 8 bits switching, c l = 30 pf) ? burst mode read: 25 ma ? simultaneous operation: 40 ma ? program/erase: 15 ma ? standby mode: 0.2 a sector architecture ? eight 8 kword sectors and one hundred twenty-six 32 kword sectors ? banks a and b each contain four 8 kword sectors and thirty-one 32 kword sectors; banks c and d each contain thirty-two 32 kword sectors sector protection ? software command sector locking ? wp# protects the last two boot sectors ? all sectors locked when v pp = v il handshaking feature ? provides host system with minimum possible latency by monitoring rdy supports common flash memory interface (cfi) software command set compatible with jedec 42.4 standards ? backwards compatible with am29f and am29lv families manufactured on 0.17 m process technology minimum 1 million erase cycle guarantee per sector 20-year data retention at 125 c ? reliable operation for the life of the system embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses data# polling and toggle bits ? provides a software method of detecting program and erase operation completion erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation hardware reset input (reset#) ? hardware method to reset the device for reading array data cmos compatible inputs and outputs package ? 44-ball very thin fbga this product has been retired and is not recommended for designs. for new designs, s29ns064j supersedes am29bds643g. please re fer to the s29ns-j family data sheet for specifi- cations and ordering information. availability of this document is retained for reference and historical purposes only.
2 am29bds643g 25692a2 may 8, 2006 data sheet general description the am29bds643g is a 64 mbit, 1.8 volt-only, simul- taneous read/write, burst mode flash memory device, organized as 4,194,304 words of 16 bits each. this device uses a single v cc of 1.7 to 1.9 v to read, program, and erase the memory array. a 12.0-volt v pp may be used for faster program performance if desired. the device can also be programmed in standard eprom programmers. at 66 mhz, the am29n643 provides a burst access of 11 ns at 30 pf with initial access times of 71 ns at 30 pf. at 54 mhz, the device provides a burst access of 13.5 ns at 30 pf with initial access times of 87.5 ns at 30 pf. at 40 mhz, the device provides a burst access of 20 ns at 30 pf with initial access times of 95 ns at 30 pf. the device operates within the industrial tempera- ture range of ?40 c to +85 c. the device is offered in the 44-ball very thin fbga package. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks. the device allows a host sys- tem to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is divided as shown in the following table: the device uses chip enable (ce#), write enable (we#), address valid (avd#) and output enable (oe#) to control asynchronous read and write opera- tions. for burst operations, the device additionally requires power saving (ps), ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to microprocessors/microcontrollers for high performance read operations. the device offers complete compatibility with the jedec 42.4 single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bit dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been com- pleted, the device automatically returns to reading array data. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the device also offers three types of data protection at the sector level. the sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector. when at v il , wp# locks the outermost sectors. finally, when v pp is at v il , all sectors are locked. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly re- duced in both modes. bank a & b sectors bank c & d sectors quantity size quantity size 48 kwords 32 32 kwords 31 32 kwords 32 mbits total 32 mbits total
may 8, 2006 25692a2 am29bds643g 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . 5 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 special handling instructions for fbga package .................... 6 input/output descriptions . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . . 9 table 1. device bus operations .......................................................9 requirements for asynchronous read operation (non-burst) 9 requirements for synchronous (burst) read operation .......... 9 continuous burst ...................................................................... 9 8-, 16-, and 32-word linear burst with wrap around ............ 10 table 2. burst address groups .......................................................10 programmable wait state ...................................................... 10 handshaking feature ............................................................. 10 power saving function ........................................................... 11 simultaneous read/write operations with zero latency ....... 11 writing commands/command sequences ............................ 11 accelerated program operation ............................................. 11 autoselect functions .............................................................. 11 automatic sleep mode ........................................................... 12 reset#: hardware reset input ............................................. 12 output disable mode .............................................................. 12 hardware data protection ...................................................... 12 low vcc write inhibit ............................................................ 12 write pulse ?glitch? protection ............................................... 12 logical inhibit .......................................................................... 12 common flash memory interface (cfi) . . . . . . . 13 table 3. cfi query identification string ..........................................13 table 4. system interface string .....................................................14 table 5. device geometry definition ..............................................14 table 6. primary vendor-specific extended query ........................15 table 7. sector address table ........................................................16 command definitions . . . . . . . . . . . . . . . . . . . . . . 20 reading array data ................................................................ 20 set configuration register command sequence ................... 20 table 8. burst modes ......................................................................20 handshaking feature ............................................................. 20 table 9. wait states for handshaking .............................................21 enable ps (power saving) mode command sequence ........ 21 sector lock/unlock command sequence .............................. 21 reset command ..................................................................... 21 autoselect command sequence ............................................ 21 program command sequence ............................................... 22 unlock bypass command sequence ..................................... 22 figure 1. program operation .......................................................... 23 chip erase command sequence ........................................... 23 sector erase command sequence ........................................ 23 erase suspend/erase resume commands ........................... 24 figure 2. erase operation.............................................................. 24 table 10. command definitions .................................................... 25 write operation status . . . . . . . . . . . . . . . . . . . . 26 dq7: data# polling ................................................................. 26 figure 3. data# polling algorithm .................................................. 26 dq6: toggle bit i .................................................................... 27 figure 4. toggle bit algorithm........................................................ 27 dq2: toggle bit ii ................................................................... 28 table 11. dq6 and dq2 indications .............................................. 28 reading toggle bits dq6/dq2 ............................................... 28 dq5: exceeded timing limits ................................................ 28 dq3: sector erase timer ....................................................... 29 table 12. write operation status ................................................... 29 absolute maximum ratings . . . . . . . . . . . . . . . . 30 figure 5. maximum negative overshoot waveform ...................... 30 figure 6. maximum positive overshoot waveform........................ 30 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. test setup....................................................................... 32 table 13. test specifications ......................................................... 32 key to switching waveforms. . . . . . . . . . . . . . . . 32 switching waveforms. . . . . . . . . . . . . . . . . . . . . . 32 figure 8. input waveforms and measurement levels...................................................................... 32 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 synchronous/burst read ........................................................ 33 figure 9. burst mode read (66 and 54 mhz) ................................ 33 figure 10. burst mode read (40 mhz) .......................................... 34 asynchronous read ............................................................... 35 figure 11. asynchronous mode read............................................ 35 figure 12. reset timings ............................................................... 36 erase/program operations ..................................................... 37 figure 13. program operation timings.......................................... 38 figure 14. chip/sector erase operations ...................................... 39 figure 15. accelerated unlock bypass programming timing........ 40 figure 16. data# polling timings (during embedded algorithm) .. 41 figure 17. toggle bit timings (during embedded algorithm)........ 41 figure 18. 8-, 16-, and 32-word linear burst address wrap around.................................................................... 42 figure 19. latency with boundary crossing (54 mhz and 66 mhz) 42 figure 20. initial access with power saving (ps) function and address boundary latency ...................................... 43 figure 21. example of extended valid address reducing wait state usage............................................................................................. 43 figure 22. back-to-back read/write cycle timings ...................... 44 erase and programming performance . . . . . . . 45 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 physical dimensions* . . . . . . . . . . . . . . . . . . . . . 46 vda044?44-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8.0 mm package ............................................... 46 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 47
4 am29bds643g 25692a2 may 8, 2006 data sheet product selector guide block diagram part number am29bds643g synchronous/burst asynchronous speed option 7g (40 mhz) 7m (54 mhz) 5k (66 mhz) speed option 7g/7m 5k v cc = 1.7 ? 1.9 v max initial access time, ns (t iacc ) 95 87.5 71 max access time, ns (t acc )7055 max burst access time, ns (t bacc ) 20 13.5 11 max ce# access, ns (t ce )7055 max oe# access, ns (t oe ) 20 13.5 11 max oe# access, ns (t oe )2011 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# v pp ce# oe# a/dq0 ? a/dq15 data latch y-gating cell matrix address latch a/dq0?a/dq15 a16?a21 rdy buffer rdy burst state control burst address counter ps buffer ps avd# clk a0?a21
may 8, 2006 25692a2 am29bds643g 5 data sheet block diagram of simultaneous operation circuit note: a0?a15 are multiplexed with dq0?dq15. v cc v ss bank b address reset# we# ce# avd# dq0?dq15 state control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq0?dq15 dq0?dq15 dq0?dq15 dq0?dq15 dq0? dq15 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# oe# oe# oe# status control a0?a21 a0?a21 a0?a21 a0?a21 a0?a21 bank c address bank d address bank a address ps rdy
6 am29bds643g 25692a2 may 8, 2006 data sheet connection diagram special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 rdy a2 a21 a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 nc b1 v cc b2 a16 b3 a20 b4 avd# b5 ps b6 reset# b7 wp# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc 44-ball very thin fbga top view, balls facing down
may 8, 2006 25692a2 am29bds643g 7 data sheet input/output descriptions a16?a21 = address inputs a/dq0? = multiplexed address/data input/output a/dq15 ce# = chip enable input. asynchronous relative to clk for the burst mode. oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v cc = device power supply (1.7 v?1.9 v). v ss =ground nc = no connect; not connected internally rdy = ready output; indicates the status of the burst read. low = data not valid at expected time. high = data valid. clk = the first rising edge of clk in conjunction with avd# low latches address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. avd# = address valid input. indicates to device that the valid address is present on the address inputs (address bits a0?a15 are multiplexed, address bits a16?a21 are address only). low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. high = device ignores address inputs ps = power saving input/output during a read operation, ps indicates whether or not the data on the outputs are inverted. low = data not inverted; high = data inverted during write or command operations, if the ps input is taken high the input data will be inverted internally; if the ps input is low the input data will not be inverted internally reset# = hardware reset input. low = device resets and returns to reading array data wp# = hardware write protect input. low = disables writes to sa132 and sa133 v pp = at 12 v, accelerates programming; automatically places device in unlock bypass mode. at v il , disables program and erase functions. should be at v ih for all other conditions. logic symbol 6 16 a/dq0? a/dq15 a16?a21 ce# oe# we# reset# clk rdy ps avd# wp# v pp
8 am29bds643g 25692a2 may 8, 2006 data sheet ordering information the order number (valid combination) is formed by the following: valid combinations valid combination configuration planned to be supported for this device. am29bds643g t 5 k va i temperature range i = industrial (?40 c to +85 c) package type va = 44-ball very thin fine-pitch grid array (fbga) 0.5 mm pitch, 9.2 x 8.0 mm package (vda044) clock rate and handshaking g = 40 mhz with handshaking m = 54 mhz with handshaking k = 66 mhz with handshaking asynchronous speed options 7 = 70 ns asynchronous read access 5 = 55 ns asynchronous read access boot code sector architecture t = top sector device number/description am29bds643g 64 megabit (4 m x 16-bit) cmos flash memory, simultaneous read/write, burst mode flash memory 1.8 volt-only read, program, and erase valid combinations order number package marking am29bds643gt7gvai n643gt7gi am29bds643gt7mvai n643gt7mi AM29BDS643GT5KVAI n643gt5ki
may 8, 2006 25692a2 am29bds643g 9 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic 0, h = logic 1, x = don?t care. requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must assert a valid address on a/dq0?a/dq15 and a16?a21, while avd# and ce# are at v il . we# should remain at v ih . note that clk must not be switching during asynchronous read operations. the rising edge of avd# latches the address, after which the system can drive oe# to v il . the data will appear on a/dq0?a/dq15. (see figure 11.) since the mem- ory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to va lid data at the output. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. requirements for synchronous (burst) read operation the device is capable of four different burst read modes (see table 8): continuous burst read; and 8-, 16-, and 32-word linear burst reads with wrap around capability. continuous burst when the device first powers up, it is enabled for asyn- chronous read operation. the device will automatically be enabled for burst mode on the first rising edge on the clk input, while avd# is held low for one clock cycle. prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst session. the system would then write the set configuration register command sequence. the system may optionally acti- vate the ps mode (see ?power saving function?) by writing the enable ps mode command sequence at this time, but note that the ps mode can only be dis- abled by a hardware reset. (see ?command defini- operation ce# oe# we# a16?2 1 a/dq0?15 reset# clk avd# asynchronous read l l h addr in i/o h h/l write l h l addr in i/o h h/l standby (ce#) h x x x high z h h/l x hardware reset x x x x high z l x x burst read operations load starting burst address l h h addr in addr in h advance burst to next address with appropriate data presented on the data bus llh x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle l h h x i/o h
10 am29bds643g 25692a2 may 8, 2006 data sheet tions? and ?programmable wait state? for further details). the initial word is output t iacc after the rising edge of the first clk cycle. subsequent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003eh. the transition from the highest address 3fffffh to 000000h is also a boundary crossing . during the time the device is out- putting the 64th word (address 00003eh, 00007eh, 0000beh, etc.), a two cycle latency occurs before data appears for the next address (address 00003fh, 00007fh, 0000bfh, etc.). the rdy output indicates this condition to the system by pulsing low. see figure 19. the device will continue to output continuous, sequen- tial burst data, wrapping around to address 000000h after it reaches the highest addressable memory loca- tion, until the system asserts ce# high, reset# low, or avd# low in conjunction with a new address. see table 1. the reset command does not terminate the burst read operation. if the host system crosses the bank boundary while reading in burst mode, and the device is not program- ming or erasing, a two-cycle latency will occur as described above. if the host system crosses the bank boundary while the device is programming or erasing, the device will provide asynch ronous read status infor- mation. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse. if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. 8-, 16-, and 32-word linear burst with wrap around the remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 2.) table 2. burst address groups as an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be 39-3a-3b-3c-3d-3e-3f-38h. the burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. programmable wait state the programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after avd# is driven active before data will be available. upon power up, the device defaults to the maximum of seven total cycles. the total number of wait states is programmable from two to seven cycles. the wait state command sequence requires three cycles; after the two unlock cycles, the third cycle address should be written according to the desired wait state as shown in table 8. address bits a11-a0 should be set to 555h, while addresses bits a16-a12 set the wait state. for further details, see ?set configuration register command sequence?. handshaking feature the handshaking feature al lows the host system to simply monitor the rdy signal from the device to deter- mine when the initial word of burst data is ready to be read. the host system should use the wait state command sequence to set the number of wait states for optimal burst mode operation (02h for 40 mhz clock, 03h for 54 and 66 mhz clock). the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. the handshaking feature may be verified by writing the autoselect command sequence to the device. see ?autoselect command sequence? for details. for optimal burst mode performance on devices without the handshaking option, the host system must set the appropriate number of wait states in the flash device depending on such factors as clock frequency, presence of a boundary crossing, or an odd or even starting address. see ?set configuration register command sequence? section for more information. the autoselect function allows the host system to dis- tinguish flash devices that have handshaking from those that do not. see the ?autoselect command sequence? section for more information. mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h, 18-1fh... 16-word 16 words 0-fh, 10-1fh, 20-2fh, 30-3fh... 32-word 32 words 00-1fh, 20-3fh, 40-5fh, 60-7fh...
may 8, 2006 25692a2 am29bds643g 11 data sheet power saving function the power save function reduces the amount of switching on the data output bus by changing the minimum number of bits possible, thereby reducing power consumption. this func tion is active only during burst mode operations. the device compares the word previously output to the system with the new word to be output. if the number of bits to be switched is 0?8 (less than half the bus width), the device simply outputs the new word on the data bus. if, however, the number of bits that must be switched is 9 or higher, the data is inverted before being output on the data bus. this effectively limits the maximum number of bits that are switched for any given read cycle to eight. the device indicates to the system whether or not the data is inverted via the ps (power saving) output. if the word on the data bus is not inverted, ps = v il ; if the word on the data bus is inverted, ps = v ih . during initial power up the ps function is disabled. to enable the ps function, the system must write the enable ps command sequence to the flash device (see the command definitions table). when the ps function is enabled, one additional clock cycle is inserted during the initial and second access of a burst sequence. see figure 20. the rdy output indi- cates this conditio n to the system. the device is also capable of receiving inverted data during command and write operations. the host system must indicate to the device via the ps input whether or not the input data is inverted. ps must be driven to v ih for inverted data, or to v il for non-inverted data. to disable the ps function, the system must hardware reset the device (drive the reset# input low). simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in one of the other three banks of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). figure 22 shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has inputs/outputs that accept both ad- dress and data information. to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writ- ing commands or data. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word, instead of four. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 7 indicates the address space that each sector occupies. the device address space is divided into four banks: banks a and b con- tain both 8 kword boot sectors in addition to 32 kword sectors, while banks c and d contain only 32 kword sectors. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. refer to the dc characteristics table for write mode current specifications. the ac characteristics section contains timing specificat ion tables and timing dia- grams for write operations. accelerated program operation the device offers accelerated program operations through the v pp input. this function is primarily in- tended to allow faster manufacturing throughput at the factory. if the system asserts v id on this input, the de- vice automatically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v id from the v pp input returns the device to normal operation. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autose lect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect functions and au- toselect command sequen ce sections for more information. standby mode when the system is not read ing or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for
12 am29bds643g 25692a2 may 8, 2006 data sheet read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enters this mode when addresse s remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset input the reset# input pr ovides a hardware method of re- setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby cur- rent will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase op- eration, the device requires a time of t ready (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a pro- gram or erase operation is not executing, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 12 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). the device offers three types of data protection at the sector level: the sector lock/unlock command sequence dis- ables or re-enables both program and erase opera- tions in any sector. when wp# is at v il , the two outermost sectors are locked. when v pp is at v il , all sectors are locked. the following hardware data protection measures pre- vent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subse- quent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one.
may 8, 2006 25692a2 am29bds643g 13 data sheet common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cf i query mode when the sys- tem writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 3?6. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 3?6. the system must write the reset command to return the device to the autoselect mode. for further information, plea se refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/over- view/cfi.html. alternatively, contact an amd representative for copies of these documents. table 3. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
14 am29bds643g 25692a2 may 8, 2006 data sheet table 4. system interface string table 5. device geometry definition addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) refer to 4dh. 1eh 0000h v pp max. voltage (00h = no v pp pin present) refer to 4eh. 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0008h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0004h number of erase block regions within device 2dh 2eh 2fh 30h 005eh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0003h 0000h 0040h 0000h erase block region 2 information 35h 36h 37h 38h 001eh 0000h 0000h 0001h erase block region 3 information 39h 3ah 3bh 3ch 0003h 0000h 0040h 0000h erase block region 4 information
may 8, 2006 25692a2 am29bds643g 15 data sheet table 6. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0005h sector protect/ unprotect scheme 05 = 29bds/n643 mode 4ah 0066h simultaneous operation number of sectors in bank 2 (uniform bank) 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = top/middle boot device, 0002h = bottom boot device, 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0020h bank d region information. x = number of sectors in bank 59h 0020h bank c region information. x = number of sectors in bank 5ah 0023h bank b region information. x = number of sectors in bank 5bh 0023h bank a region information. x = number of sectors in bank 5ch 0001h process technology. 00h = 0.23 m, 01h = 0.17 m
16 am29bds643g 25692a2 may 8, 2006 data sheet table 7. sector address table sector sector size (x16) address range bank d sa0 32 kwords 000000h?007fffh sa1 32 kwords 008000h?00ffffh sa2 32 kwords 010000h?017fffh sa3 32 kwords 018000h?01ffffh sa4 32 kwords 020000h?027fffh sa5 32 kwords 028000h?02ffffh sa6 32 kwords 030000h?037fffh sa7 32 kwords 038000h?03ffffh sa8 32 kwords 040000h?047fffh sa9 32 kwords 048000h?04ffffh sa10 32 kwords 050000h?057fffh sa11 32 kwords 058000h?05ffffh sa12 32 kwords 060000h?067fffh sa13 32 kwords 068000h?06ffffh sa14 32 kwords 070000h?077fffh sa15 32 kwords 078000h?07ffffh sa16 32 kwords 080000h?087fffh sa17 32 kwords 088000h?08ffffh sa18 32 kwords 090000h?097fffh sa19 32 kwords 098000h?09ffffh sa20 32 kwords 0a0000h?0a7fffh sa21 32 kwords 0a8000h?0affffh sa22 32 kwords 0b0000h?0b7fffh sa23 32 kwords 0b8000h?0bffffh sa24 32 kwords 0c0000h?0c7fffh sa25 32 kwords 0c8000h?0cffffh sa26 32 kwords 0d0000h?0d7fffh sa27 32 kwords 0d8000h?0dffffh sa28 32 kwords 0e0000h?0e7fffh sa29 32 kwords 0e8000h?0effffh sa30 32 kwords 0f0000h?0f7fffh sa31 32 kwords 0f8000h?0fffffh
may 8, 2006 25692a2 am29bds643g 17 data sheet bank c sa32 32 kwords 100000h?107fffh sa33 32 kwords 108000h?10ffffh sa34 32 kwords 110000h?117fffh sa35 32 kwords 118000h?11ffffh sa36 32 kwords 120000h?127fffh sa37 32 kwords 128000h?12ffffh sa38 32 kwords 130000h?137fffh sa39 32 kwords 138000h?13ffffh sa40 32 kwords 140000h?147fffh sa41 32 kwords 148000h?14ffffh sa42 32 kwords 150000h?157fffh sa43 32 kwords 158000h?15ffffh sa44 32 kwords 160000h?167fffh sa45 32 kwords 168000h?16ffffh sa46 32 kwords 170000h?177fffh sa47 32 kwords 178000h?17ffffh sa48 32 kwords 180000h?187fffh sa49 32 kwords 188000h?18ffffh sa50 32 kwords 190000h?197fffh sa51 32 kwords 198000h?19ffffh sa52 32 kwords 1a0000h?1a7fffh sa53 32 kwords 1a8000h?1affffh sa54 32 kwords 1b0000h?1b7fffh sa55 32 kwords 1b8000h?1bffffh sa56 32 kwords 1c0000h?1c7fffh sa57 32 kwords 1c8000h?1cffffh sa58 32 kwords 1d0000h?1d7fffh sa59 32 kwords 1d8000h?1dffffh sa60 32 kwords 1e0000h?1e7fffh sa61 32 kwords 1e8000h?1effffh sa62 32 kwords 1f0000h?1f7fffh sa63 32 kwords 1f8000h?1fffffh bank b sa64 32 kwords 200000h?207fffh sa65 32 kwords 208000h?20ffffh sa66 32 kwords 210000h?217fffh sa67 32 kwords 218000h?21ffffh sa68 32 kwords 220000h?227fffh sa69 32 kwords 228000h?22ffffh sa70 32 kwords 230000h?237fffh sa71 32 kwords 238000h?23ffffh sa72 32 kwords 240000h?247fffh sa73 32 kwords 248000h?24ffffh sa74 32 kwords 250000h?257fffh sa75 32 kwords 258000h?25ffffh table 7. sector address table (continued) sector sector size (x16) address range
18 am29bds643g 25692a2 may 8, 2006 data sheet bank b (continued) sa76 32 kwords 260000h?267fffh sa77 32 kwords 268000h?26ffffh sa78 32 kwords 270000h?277fffh sa79 32 kwords 278000h?27ffffh sa80 32 kwords 280000h?287fffh sa81 32 kwords 288000h?28ffffh sa82 32 kwords 290000h?297fffh sa83 32 kwords 298000h?29ffffh sa84 32 kwords 2a0000h?2a7fffh sa85 32 kwords 2a8000h?2affffh sa86 32 kwords 2b0000h?2b7fffh sa87 32 kwords 2b8000h?2bffffh sa88 32 kwords 2c0000h?2c7fffh sa89 32 kwords 2c8000h?2cffffh sa90 32 kwords 2d0000h?2d7fffh sa91 32 kwords 2d8000h?2dffffh sa92 32 kwords 2e0000h?2e7fffh sa93 32 kwords 2e8000h?2effffh sa94 32 kwords 2f0000h?2f7fffh sa95 8 kwords 2f8000h?2f9fffh sa96 8 kwords 2fa000h?2fbfffh sa97 8 kwords 2fc000h?2fdfffh sa98 8 kwords 2fe000h?2fffffh bank a sa99 32k words 300000h?307fffh sa100 32k words 308000h?30ffffh sa101 32k words 310000h?317fffh sa102 32k words 318000h?31ffffh sa103 32k words 320000h?327fffh sa104 32k words 328000h?32ffffh sa105 32k words 330000h?337fffh sa106 32k words 338000h?33ffffh sa107 32k words 340000h?347fffh sa108 32k words 348000h?34ffffh sa109 32k words 350000h?357fffh sa110 32k words 358000h?35ffffh sa111 32k words 360000h?367fffh sa112 32k words 368000h?36ffffh sa113 32k words 370000h?377fffh sa114 32k words 378000h?37ffffh sa115 32k words 380000h?387fffh sa116 32k words 388000h?38ffffh table 7. sector address table (continued) sector sector size (x16) address range
may 8, 2006 25692a2 am29bds643g 19 data sheet bank a (continued) sa117 32k words 390000h?397fffh sa118 32k words 398000h?39ffffh sa119 32k words 3a0000h?3a7fffh sa120 32k words 3a8000h?3affffh sa121 32k words 3b0000h?3b7fffh sa122 32k words 3b8000h?3bffffh sa123 32k words 3c0000h?3c7fffh sa124 32k words 3c8000h?3cffffh sa125 32k words 3d0000h?3d7fffh sa126 32k words 3d8000h?3dffffh sa127 32k words 3e0000h?3e7fffh sa128 32k words 3e8000h?3effffh sa129 32k words 3f0000h?3f7fffh sa130 8k words 3f8000h?3f9fffh sa131 8k words 3fa000h?3fbfffh sa132 8k words 3fc000h?3fdfffh sa133 8k words 3fe000h?3fffffh table 7. sector address table (continued) sector sector size (x16) address range
20 am29bds643g 25692a2 may 8, 2006 data sheet command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 10 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the rising edge of avd#. all data is latched on the rising edge of we#. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector. after com- pleting a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for asynchronous read operation (non-burst) and requirements for synchronous (burst) read operation in the device bus operations section for more information. the asynchronous read and synchronous/burst read tables provide the read parameters, and figures 9 and 11 show the timings. set configuration register command se- quence the configuration register command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. the first two cycles of the command sequence are for unlock purposes. on the third cycle, the system should write c0h to the address associated with the intended wait state setting (see table 8). address bits a16?a12 determine the setting. note that addresses a19?a17 are shown as ?0? but are actually don?t care. table 8. burst modes note: the burst mode is set in the third cycle of the set wait st ate command sequence. upon power up, the device defaults to the maximum seven cycle wait state setting. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default setting. handshaking feature the host system should set address bits a16?a12 to ?00010? for a clock frequency of 40 mhz or to ?00011? for a clock frequency of 54 or 66 mhz, assuming con- tinuous burst is desired in both cases. table 9 describes the typical number of clock cycles (wait states) for various conditions. burst mode third cycle addresses for wait states wait states012345 clock cycles234567 continuous 00555h 01555h 02555h 03555h 04555h 05555h 8-word linear 08555h 09555h 0a555h 0b555h 0c555h 0d555h 16-word linear 10555h 11555h 12555h 13555h 14555h 15555h 32-word linear 18555h 19555h 1a555h 1b555h 1c555h 1d555h
may 8, 2006 25692a2 am29bds643g 21 data sheet table 9. wait states for handshaking * in the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3eh). the autoselect function allows the host system to determine whether the flash device is enabled for handshaking. see the ?autoselect command sequence? section for more information. enable ps (power saving) mode command sequence the enable ps (power saving) mode command sequence is required to set the device to the ps mode. on power up, the power saving mode is disabled. the command sequence consists of two unlock cycles fol- lowed by a command cycle in which the address and data should 555h/70h, respectively. the ps mode remains enabled until the device is hardware reset (either device is powered down or reset# is asserted low). sector lock/unloc k command sequence the sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. when the device is first powered up, all sectors are locked. to unlock a sector, the system must write the sector lock/unlock command sequence. two cycles are first written: addresses are don?t care and data is 60h. during the third cycle, the sector address (sla) and unlock command (60h) is written, while specifying with address a6 whether that sector should be locked (a6 = v il ) or unlocked (a6 = v ih ). after the third cycle, the syst em can continue to lock or unlock additional cycles, or exit the sequence by writing f0h (reset command). note that the last two outermost boot sectors can be locked by taking the wp# signal to v il . also, if v pp is at v il all sectors are locked; if the v pp input is at v pp , all sectors are unlocked. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is com- plete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mo de, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 10 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively program- ming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. th is is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters the autoselect mode. the system may read at any address within the same bank any number of times without ini- tiating another autoselect command sequence. the fol- lowing table describes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address, and sa represents conditions at address typical no. of clock cycles after avd# low 40 mhz 54/66 mhz initial address is even 4 5 initial address is odd 5 6 initial address is even, and is at boundary crossing* 67 initial address is odd, and is at boundary crossing* 78
22 am29bds643g 25692a2 may 8, 2006 data sheet the sector address. the device id is read in three cycles. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by monitoring dq7 or dq6/dq2. refer to the writ e operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to prima- rily program to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 10 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the v pp input. when the system asserts v pp on this input, the device automatically enters the unlock bypass mode. the sy stem may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the v pp input to accelerate the operation. figure 1 illustrates the algorithm for the program oper- ation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 13 for timing diagrams. description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2202h device id, word 3 (ba) + 0fh 2200h sector block lock/unlock (sa) + 02h 0001 (locked), 0000 (unlocked) handshaking (ba) + 03h 43h
may 8, 2006 25692a2 am29bds643g 23 data sheet figure 1. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7 or dq6/dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles cycles in length instead of six cycles. see table 10 for details on the unlock bypass command sequences. figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 14 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sec- tors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 for program command sequence.
24 am29bds643g 25692a2 may 8, 2006 data sheet when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7 or dq6/ dq2 in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 14 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, program data to, any sector not selected for erasure. the system may also lock or unlock any sec- tor while the erase operation is suspended. the sys- tem must not write the sector lock/unlock command to sectors selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase op- eration, including the minimum 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) the system may also lock or unlock any sector while in the erase-suspend-read mode. reading at any address within erase-suspended sectors produces status infor- mation on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect functions an d autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 2. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
may 8, 2006 25692a2 am29bds643g 25 data sheet table 10. command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. ba = address of the bank (a21, a20) that is being switched to autoselect mode, is in bypass mode, or is being erased. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register set by address bits a16?a12. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a12 are don?t cares. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must read device ids across the 4th, 5th, and 6th cycles, the system must provide the bank address. see the autoselect command sequence section for more information. 9. the data is 0000h for an unlocked sector and 0001h for a locked sector 10. the data is 0043h for handshaking enabled. 11. the unlock bypass command sequence is required prior to this command sequence. 12. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 15. the addresses in the third cycle must contain, on a12?a16, the additional wait counts to be set. see ?set configuration register command sequence?. 16. command is valid when device is ready to read array data or when device is in autoselect moe. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 (ba)555 90 (ba)x00 0001 device id 6 555 aa 2aa 55 (ba)555 90 (ba)x01 227e (ba) x0e 2202 (ba) x0f 2200 sector lock verify (note 9) 4 555 aa 2aa 55 (sa)555 90 (sa)x02 0000 0001 handshaking option (note 10) 4 555 aa 2aa 55 (ba)555 90 (ba)x03 0042 0043 program 4 555 aa 2aa 55 555 a0 pa data unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 ba 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 13) 1 ba b0 erase resume (note 14) 1 ba 30 sector lock/unlock 3 xxx 60 xxx 60 sla 60 set configuration register (note 15) 3 555 aa 2aa 55 (cr)555 c0 enable ps mode 3 555 aa 2aa 55 555 70 cfi query (note 16) 1 55 98
26 am29bds643g 25692a2 may 8, 2006 data sheet write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 12 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algo- rithm is in progress or completed, or whether a bank is in erase suspend. data# pollin g is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pr ogram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on succes- sive read cycles. table 12 shows the outputs for data# polling on dq7. figure 3 shows the data# po lling algorithm. figure 16 in the ac characteristics section shows the data# polling timing diagram. figure 3. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
may 8, 2006 25692a2 am29bds643g 27 data sheet rdy: ready the rdy is a dedicated output that indicates (when at logic low) the syste m should wait until rdy returns high before expecting the next word of data. rdy functions only while reading data in burst mode. the following conditions cause the rdy output to be low: during the initial acce ss (in burst mode); after the boundary that occurs every 64 words beginning with the 63rd address, 3eh; and when the clock frequency is less than 6 mhz (in which case rdy is low every third clock). the rdy pin will also switch during status reads if there is a clock signal at the clk input. if rdy goes low, it indicates that the status data is not yet valid and that the system should wait until rdy returns high. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. note that oe# must be low during toggle bit status reads. when the operation is com- plete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the de vice is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 4 (toggle bit flowchart), dq6: toggle bit i (description), figure 17 (toggle bit timing diagram), and table 11 (compares dq2 and dq6). figure 4. toggle bit algorithm start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
28 am29bds643g 25692a2 may 8, 2006 data sheet dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. note that oe# must be low during toggle bit status reads. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode informa- tion. refer to table 12 to compare outputs for dq2 and dq6. see the following for additional information: figure 4 (toggle bit flowchart), dq6: toggle bit i (description), figure 17 (toggle bit timing diagram), and table 11 (compares dq2 and dq6). table 11. dq6 and dq2 indications reading toggle bits dq6/dq2 refer to figure 4 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bi t is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has com- pleted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed th e operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). dq5: exceeded ti ming limits dq5 indicates whether the program or erase time has exceeded a specified intern al pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
may 8, 2006 25692a2 am29bds643g 29 data sheet halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence sec- tion. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 12 shows the status of dq3 relative to the other status bits. table 12. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addr esses a non-busy bank. 4. the system may read either asynchronously or synchronously (b urst) while in erase suspend. rdy will function exactly as in non-erase-suspended mode. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode erase-suspend- read (note 4) erase suspended sector 1 no toggle 0 n/a toggle non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
30 am29bds643g 25692a2 may 8, 2006 data sheet absolute maximum ratings storage temperature . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground, all inputs and i/os except v pp (note 1) . . . . . . . . . ?0.5 v to v cc + 0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v pp (note 2) . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v output short circuit current (note 3) . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, input at i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns during voltage transitions inputs might overshooot to v cc +0.5 v for periods up to 20 ns. see figure 5. maximum dc voltage on output and i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 6. 2. minimum dc input voltage on v pp is ?0.5 v. during voltage transitions, v pp may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 5. maximum dc input voltage on v pp is +12.5 v which may overshoot to +13.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short ci rcuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device reli- ability. figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.7 v v cc max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.9 v operating ranges define those li mits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.9 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v 20 ns 2.0 v
may 8, 2006 25692a2 am29bds643g 31 data sheet dc characteristics cmos compatible note: 1. maximum i cc specifications are tested with v cc = v cc max. 2. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . 5. total current during accelerated programming is the sum of v pp and v cc currents. 6. specifications assume 8 i/os switching. parameter description test cond itions (note 1) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current (note 6) ce# = v il , oe# = v il 25 30 ma i cc1 v cc active asynchronous read current ce# = v il , oe# = v ih 5 mhz 12 16 ma 1 mhz 3.55ma i cc2 v cc active write current (note 3) ce# = v il , oe# = v ih , v pp = v ih 15 40 ma i cc3 v cc standby current (note 4) ce# = v ih , reset# = v ih 0.2 10 a i cc4 v cc reset current reset# = v il, clk = v il 0.2 10 a i cc5 v cc active current (read while write) ce# = v il , oe# = v il 40 60 ma i pp accelerated program current (note 5) ce# = v il , oe# = v ih, v pp = 12.0 0.5 v v pp 715ma v cc 510ma v il input low voltage ?0.5 0.4 v v ih input high voltage v cc ? 0.4 v cc + 0.2 v v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min v cc ? 0.1 v v id voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
32 am29bds643g 25692a2 may 8, 2006 data sheet test conditions table 13. test specifications key to switching waveforms switching waveforms c l device under te s t figure 7. test setup test condition all speeds unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v cc v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v output measurement level input v cc /2 v cc /2 figure 8. input waveforms and measurement levels
may 8, 2006 25692a2 am29bds643g 33 data sheet ac characteristics synchronous/burst read notes: 1. figure shows total number of clock set to five. 2. figure shows that ps (power saving mode) has been enabled; one additional wait state occurs during initial data da. latency is not present if ps is not enabled. 3. if any burst address occurs at a 64-word boundary, two add itional clock cycles are inserted, and is indicated by rdy. figure 9. burst mode read (66 and 54 mhz) parameter description 7g (40 mhz) 7m (54 mhz) 5k (66 mhz) unit jedec standard t iacc initial access time max 95 87.5 71 ns t bacc burst access time valid clock to output delay max 20 13.5 11 ns t avds avd# setup time to clk min 5 4 ns t avdh avd# hold time from clk min 7 6 ns t avdo avd# high to oe# low min 0 0 ns t acs address setup time to clk min 5 4 ns t ach address hold time from clk min 7 6 ns t bdh data hold time from next clock cycle max 4 4 ns t oe output enable to data, ps, or rdy valid max 20 13.5 11 ns t cez chip enable to high z max 10 10 ns t oez output enable to high z max 10 10 ns t ces ce# setup time to clk min 5 4 ns t rdys rdy setup time to clk min 5 4 ns t racc ready access time from clk max 20 13.5 11 ns da da + 1 da + 2 da + n oe# a/dq0: a/dq15 a16: a21 aa avd# rdy clk ce# t ces t acs t avds t avdh t avdo t ach t bacc t racc t oe t oez t cez t iacc t ryds t bdh aa 5 cycles for initial access shown. programmable wait state function is set to 03h. 1 cycle wait state when ps enabled 18.5 ns typ. (54 mhz) hi-z hi-z hi-z
34 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics notes: 1. figure shows total number of clock cycles set to four. 2. figure shows that ps (power saving mode) has been enabled; one additional wait state occurs during initial data da. latency is not present if ps is not enabled. 3. if any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by rdy. figure 10. burst mode read (40 mhz) da da + 1 da + 2 da + n oe# a/dq0: a/dq15 a16: a21 aa avd# rdy clk ce# t ces t acs t avds t avdh t avdo t ach t bacc t oe t oez t cez t iacc t bdh aa 4 cycles for initial access shown. programmable wait state function is set to 02h. 1 cycle wait state when ps enabled 25 ns typ. t racc hi-z hi-z hi-z t ryds
may 8, 2006 25692a2 am29bds643g 35 data sheet ac characteristics asynchronous read note: not 100% tested. note: ra = read address, rd = read data. figure 11. asynchronous mode read parameter description 7g/7m 5k unit jedec standard t ce access time from ce# low max 70 55 ns t acc asynchronous access time max 70 55 ns t avdp avd# low time min 12 11 ns t aavds address setup time to rising edge of avd min 5 4 ns t aavdh address hold time from rising edge of avd min 7 6 ns t oe output enable to output valid max 20 11 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t ce we# a16 - a21 ce# oe# valid rd t acc t oeh t oe a/dq0: a/dq15 t oez t aavdh t avdp t aavds avd# ra ra
36 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t readyw reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms t readyw ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 12. reset timings
may 8, 2006 25692a2 am29bds643g 37 data sheet ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. does not include the preprogramming time. parameter description 7g/7m 5k unit jedec standard t avav t wc write cycle time (note 1) min 80 45 ns t avwl t as address setup time min 5 4 ns t wlax t ah address hold time min 7 6 ns t avdp avd# low time min 12 11 ns t dvwh t ds data setup time min 45 25 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write typ 0 ns t elwl t cs ce# setup time typ 0 ns t wheh t ch ce# hold time typ 0 ns t wlwh t wp /t wrl write pulse width typ 50 25 ns t whwl t wph write pulse width high typ 30 20 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) typ 11.5 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (notes 2, 3) typ 0.4 sec t vpp v pp rise and fall time min 500 ns t vps v pp setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s
38 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refe r to status of program operation. 3. a16?a21 are don?t care during command sequence unlock cycles. figure 13. program operation timings oe# ce# a/dq0: a/dq15 a16:a21 avd we# clk v cc 555h a0h pd t as t wp t ah t wc t wph pa pa t vcs t cs t dh t ch in progress t whwh1 va va complete va va program command sequence (last two cycles) read status data ps in ps t ds v ih v il t avdp valid only when ps mode is enabled
may 8, 2006 25692a2 am29bds643g 39 data sheet ac characteristics notes: 1. sa is the sector address for sector erase. 2. address bits a16?a21 are don?t cares during unlock cycles in the command sequence. figure 14. chip/sector erase operations oe# ce# a/dq0: a/dq15 a16:a21 avd we# clk v cc 2aah 55h 30h t as t wp t ah t wc t wph sa sa t vcs t cs t dh t ch in progress t whwh2 va va complete va va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp
40 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operation. figure 15. accelerated unlock bypass programming timing ce# avd# we# a16:a21 a/dq0: a/dq15 ce# v pp don't care don't care a0h pa pa pd v id 1 s v il or v ih t vpp t vps
may 8, 2006 25692a2 am29bds643g 41 data sheet ac characteristics notes: 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determi ne status. when the embedded algorithm operation is complete, and data# polling will output true data. figure 16. data# polling timings (during embedded algorithm) notes: 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determi ne status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. figure 17. toggle bit timings (during embedded algorithm) we# ce# oe# t oe a16:a21 a/dq0: a/dq15 avd t oeh t ce t ch t oez t cez status data status data t acc va va va va we# ce# oe# t oe a16:a21 a/dq0: a/dq15 avd t oeh t ce t ch t oez t cez status data status data t acc va va va va
42 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics note: 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. figure 18. 8-, 16-, and 32-word linear burst address wrap around note: cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure 19. latency with boundary crossing (54 mhz and 66 mhz) clk a ddress (hex) d0 d1 d2 a/dq0: a/dq15 oe#, ce# address wraps back to beginning of address group. 39 39 3a 3b 3c 3d 3e 3f 38 initial access v il v ih avd# v il v ih d3 d4 d5 d6 d7 clk address (hex) c59 c60 c61 c62 c62 c62 c63 c64 c65 c66 d59 d60 d61 d62 d63 d64 d65 d66 (stays high) avd# rdy a/dq0: a/dq15 oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003eh: 00007eh, 0000beh, etc. address 000000h is also a boundary crossing. 3b 3c 3d 3e 3e 3e 3f 40 41 42 latency t racc
may 8, 2006 25692a2 am29bds643g 43 data sheet ac characteristics note: devices should be programmed with wait states as discuss ed in the ?programmable wait state? section on page 10. figure 20. initial access with power saving (ps) function and address boundary latency note: if t avdsm > 1 clk cycle, wait state usage is reduced. figure show s 40 mhz clock, handshaking enabled. wait state usage is 4 clock cycles instead of 5. note that t avdsm must be less than 76 s for burst operation to begin. figure 21. example of extended valid address reducing wait state usage clk avd# rdy ps address high-z high-z a/dq0: a/dq15 ps oe# d0 d1 d2 ps1 ps2 device is programmable from 2 to 7 total cycles during initial access (here, programmable wait state function is set to 04h; 6 cycles total) ps high if data is inverted, low if data is not inverted 2 additional wait states if address is at boundary 1 additional wait state to indicate ps is enabled avd# low with clock present enables burst read mode address a16:a21 boundary latency t oe clk avd# rdy high-z a/dq oe# ce# d0 d1 d2 t iacc2 t avdsm addresses
44 am29bds643g 25692a2 may 8, 2006 data sheet ac characteristics note: breakpoints in waveforms indicate that system may alternatel y read array data from the ?non-busy bank? while checking the status of the program or erase operat ion in the ?busy? bank. the system should re ad status twice to ensure valid informatio n. figure 22. back-to-back read/write cycle timings oe# ce# we# t oeh a/dq0: a/dq15 a16: a21 avd# pd/30h pa/sa aah 555h ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra ra ra rd t wph
may 8, 2006 25692a2 am29bds643g 45 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 1 million cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.8 v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1 million cycles. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 32 kword 0.4 5 s excludes 00h programming prior to erasure (note 4) 8 kword 0.4 5 chip erase time 54 s word programming time 11.5 210 s excludes system level overhead (note 5) accelerated word programming time 4 120 s chip programming time (note 3) 48 144 s excludes system level overhead (note 5) accelerated chip programming time 16 48 s parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
46 am29bds643g 25692a2 may 8, 2006 data sheet physical dimensions* vda044?44-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8.0 mm package * for reference only. bsc is an ansi standard for basic space centering. a m m c c 0.05 0.15 b 1.00 sd 1.00 a1 corner 7 7 6 b e1 d1 se e bottom view nf2 10 9 a c d b 87654321 nf3 nf4 nf1 top view 0.50 ref 1.00 +0.20 -0.50 0.50 ref -0.50 1.00 +0.20 d a e a1 id b side view a seating plane c 0.10 a2 a1 c c 0.08 nf1-4 n/a 9.20 mm x 8.00 mm package vda 044 nom. - - - 1.00 - 0.78 max. 9.20 bsc. 8.00 bsc. 10 - min. 0.64 0.20 4.50 bsc. 1.50 bsc. 4 44 0.30 0.35 0.25 bsc. a 0.25 0.50 bsc. me d e jedec package symbol a a2 a1 md d1 e1 b n note package outline type depopulated solder balls row matrix size e direction ball footprint ball pitch body size ball height body size body thickness overall thickness ball diameter row matrix size d direction total ball count ball footprint solder ball placement e sd/se notes unless otherwise specified: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum z . 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls.
may 8, 2006 25692a2 am29bds643g 47 data sheet revision summary revision a (november 1, 2001) initial release. revision a+1 (nov ember 9, 2001) program command sequence; table 10, command definitions deleted references to unlock bypass chip and sector erase commands. ac characteristics, erase and program operations corrected t whwh1 and t whwh2 to match same specifi- cations elsewhere in document. physical dimensions replaced drawing with updated version. revision a2 (may 8, 2006) added migration/obsolescence information. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and pr evention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those product. copyright ? 2001?2006 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

▲Up To Search▲

Price & Availability of AM29BDS643GT5KVAI

	To Download AM29BDS643GT5KVAI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .